1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly, to a circuit for driving a liquid crystal display device.
2. Discussion of the Related Art
With the progress of information-dependent society, the demand for various display devices has increased. To meet such a demand, efforts have recently been made to research and develop flat panel display devices such as liquid crystal displays (LCDs), plasma display panels (PDPs), electro-luminescent displays (ELDs), vacuum fluorescent displays (VFDs), and the like. Some types of such flat panel display devices are being practically applied to various appliances for display purposes.
In particular, LCDs have been used as a substitute for cathode ray tubes (CRTs) in association with mobile image display devices owing to their characteristics and advantages of superior picture quality, lightness, thinness, and low power consumption. Thus, LCDs are currently most widely used. Various applications of LCDs are being developed in association with not only mobile image display devices such as monitors of notebook computers, but also monitors of TVs to receive and display broadcast signals, and monitors of laptop computers.
Therefore, the successful application of LCDs to diverse image display devices depends on the ability of LCDs to realize desired high picture quality including high resolution, high brightness, large display area, and the like, while maintaining desired characteristics of lightness, thinness, and low power consumption.
Such an LCD mainly includes a liquid crystal panel for displaying an image signal, and a driving circuit for applying a drive signal to the liquid crystal panel.
Although not shown in the drawings, the liquid crystal panel is comprised of two transparent substrates (glass substrates) bonded to each other so as to have a certain space therebetween, and a liquid crystal layer formed between the two transparent substrates.
In one of the two transparent substrates is formed a plurality of gate lines arranged at certain regular intervals, a plurality of data lines arranged perpendicularly to the gate lines for defining pixel areas, a plurality of pixel electrodes formed respectively in the pixel areas, and a plurality of thin film transistors formed respectively at intersections of the gate lines and the data lines and each serving to transfer a data signal on an associated one of the data lines to an associated one of the pixel electrodes in response to a gate signal on an associated one of the gate lines.
As a result, whenever a turn-on signal is sequentially applied to the gate lines, a data signal is applied to a pixel electrode of the corresponding gate line so as to display an image.
Here, the image displayed on the liquid crystal panel is composed of one frame when it is a still image, and a plurality of frames when it is a moving image in which a plurality of sequential still images are successively expressed.
In the case where the displayed image is a moving image, the liquid crystal varies successively with the magnitudes of data signals corresponding respectively to frames of the moving image.
That is, in order to express one moving image with five frames on the liquid crystal panel, the liquid crystal varies successively with the magnitudes of data signals corresponding respectively to the five frames because the magnitudes of the data signals are different.
The magnitude of the data signal of each frame is expressed on the liquid crystal layer as the level of a gray-scale voltage so as to vary the orientation of liquid crystal molecules of the liquid crystal layer. Because the liquid crystal molecules have dielectric anisotropy, permittivity thereof varies if the longer-axis direction thereof varies. Subsequently, the level of a gray scale voltage to the liquid crystal layer varies with the permittivity of the liquid crystal molecules of the liquid crystal layer, resulting in a significant reduction in response speed of the liquid crystal molecules.
Namely, in the case where the gray scale voltage to the liquid crystal is to be changed from a low level to high level (or vice versa), it can reach the desired level, not at once, but after the lapse of several frames from a current frame, because the gray scale voltage of a data signal of the current frame is influenced by the gray scale voltage of a data signal of a previous frame.
For example, in order to express one moving image composed of two successive frames, the liquid crystal must be changed to the level of a gray scale voltage corresponding to an image of the second frame at once after being maintained in a state changed to the level of a gray scale voltage corresponding to an image of the first frame. However, provided that the response speed of the liquid crystal molecules is reduced due to factors as mentioned above, the liquid crystal will be unable to express the level of the gray scale voltage corresponding to the image of the second frame within a period of one frame.
This phenomenon can be represented as the display of a vague latent image of the first frame of the previous period overlapping with the image of the second frame on the liquid crystal panel.
Accordingly, research has been conducted into a method for improving the response speed of the liquid crystal molecules by over-driving the magnitude of a gray scale voltage setting data signal to a value higher than the normal value.
A conventional liquid crystal display device with an over-driving circuit will hereinafter be described with reference to the annexed drawings.
FIG. 1 is a block diagram showing the configuration of a conventional liquid crystal display device with an over-driving circuit.
The conventional liquid crystal display device comprises, as shown in FIG. 1, a liquid crystal panel 11 having a plurality of gate lines G and a plurality of data lines D arranged perpendicularly to each other for defining pixel areas in the form of a matrix, and a driving circuit 12 for supplying a drive signal and a data signal to the liquid crystal panel 11.
The driving circuit 12 includes an external storage unit 25 for storing a look-up table (LUT) for over-driving, and a direct current-direct current (DC-DC) converter 24 for receiving a voltage from a system through a connector 22, stepping up or down the received voltage, outputting the resulting drive voltages Vcc and Vdd necessary to respective components, and outputting a gate low voltage signal VGL and a gate high voltage signal VGH in response to an enable signal from a timing controller 23. The timing controller 23 is adapted to, upon power-on, read the LUT from the external storage unit (for example, an electrically erasable programmable read only memory (EEPROM)) 25, store the read LUT in an over-driving circuit (ODC) 31 provided therein, correct a video signal inputted from the system into a video signal Do for over-driving on the basis of the LUT, output the corrected video signal Do, and output the enable signal to the DC-DC converter 24. The driving circuit further includes a gate driver 11a for generating a scan pulse in response to the gate high voltage signal VGH and gate low voltage signal VGL, outputted from the DC-DC converter 24 in response to the enable signal from the timing controller 23, and supplying the generated scan pulse sequentially to the gate lines G of the liquid crystal panel 11, and a data driver 11b for receiving the corrected video signal Do outputted from the timing controller 23, digital/analog-converting the received video signal into a corrected analog data signal and supplying the corrected data signal to each of the data lines D of the liquid crystal panel 11.
The timing controller 23 further includes a power control generating logic block 32 for receiving the drive voltage and outputting the enable signal, and a protocol block 33 for providing an Inter IC bus (“I2C”) communication protocol when the timing controller 23 communicates with the external storage unit 25 in an I2C protocol manner to read a checksum of data of the look-up table stored in the external storage unit 25.
Two active wires SCL(Clock) and SDA(Data) for the aforementioned communication are connected between the protocol block 33 and the external storage unit 25.
An R, G, B video signal outputted from the system is inputted to the timing controller 23 through the connector 22 sequentially on a frame-by-frame basis. The ODC 31 compares a video signal of a current frame with a video signal of a previous frame on the basis of the look-up table and outputs a corrected video signal Do of a magnitude higher than that of the current frame video signal as a result of the comparison.
That is, in the look-up table, values corresponding to the video signal of the previous frame and the video signal of the current frame are arranged in an x-axis and a y-axis. Also, a value corresponding to the corrected video signal Do is defined at an intersection of the x-axis and y-axis. As a result, the timing controller 23 reads a value at a crossing point of the value of the inputted video signal of the previous frame and the value of the inputted video signal of the current frame from the look-up table and outputs the corrected video signal Do based on the read value.
Therefore, a pixel electrode which receives a corrected data signal, outputted from the data driver 11b on the basis of the corrected video signal Do, over-drives the liquid crystal with a higher gray scale voltage.
A more detailed description will hereinafter be given of the over-driving circuit 31 in the timing controller 23.
FIG. 2 is a block diagram of the over-driving circuit in the conventional liquid crystal display device.
An R, G, B video signal outputted from the system is inputted to the timing controller (see 23 in FIG. 1) through the connector (see 22 in FIG. 1) sequentially on a frame-by-frame basis.
The over-driving circuit of the conventional liquid crystal display device includes, as shown in FIG. 2, an internal storage unit (for example, a static random access memory (SRAM)) 31 for storing the look-up table (LUT) stored in the external storage unit 25, first and second frame memories 33a and 33b for alternately storing the R, G, B video data sequentially inputted from the system on a frame-by-frame basis, and an FFD circuit 33c for receiving video data of a current frame inputted from the system and video data of a previous frame stored in the first or second frame memory 33a or 33b, comparing the received video data of the two frames with each other and outputting a corrected video signal Do of the current frame video data according to the look-up table stored in the internal storage unit 31 as a result of the comparison.
The first and second frame memories 33a and 33b are adapted to alternately store data of one frame in a write mode and output the stored frame data in a read mode. That is, currently inputted R, G, B video data is stored in the first frame memory 33a and video data of a previous frame stored in the second frame memory 33b is read. Next, currently inputted R, G, B video data is stored in the second frame memory 33b and video data of a previous frame stored in the first frame memory 33a is read. This operation is repeated.
An over-driving operation of the conventional over-driving circuit with the above-stated configuration will hereinafter be described.
First, the manufacturer or user creates and stores the look-up table in the external storage unit 25. That is, the look-up table is created by arranging values corresponding to a video signal of a previous frame and a video signal of a current frame in an x-axis and a y-axis, and inputting a value corresponding to a corrected video signal Do at an intersection of the x-axis and y-axis.
The look-up table is created in this manner and is then stored in the external storage unit 25.
Under this condition, whenever power is turned on, the timing controller 23 reads the look-up table stored in the external storage unit 25 and stores it in the ODC 31.
At the time that R, G, B data is inputted from the system, the timing controller 23 stores the inputted R, G, B data in the first frame memory 33a and reads data of a previous frame stored in the second frame memory 33b. Next, the timing controller 23 stores currently inputted R, G, B data in the second frame memory 33b and reads data of a previous frame stored in the first frame memory 33a. 
Then, the FFD circuit 33c retrieves a value at a crossing point of the value of the video signal of the previous frame and the value of the video signal of the current frame from the look-up table and outputs a corrected video signal Do based on the retrieved value. Then, the data driver 11b applies the corrected video signal Do to each pixel electrode so as to over-drive the liquid crystal with a higher gray scale voltage.
On the other hand, a backlight unit is placed on the back of a liquid crystal panel of a transmissive liquid crystal display device or along the edge thereof to provide constant light for display under no influence of external light. Such backlight units may be roughly classified into an edge-type backlight unit wherein lamps are disposed along the edge of the liquid crystal panel to supply light to the panel, and a direct-backing type backlight unit wherein lamps are disposed directly on the back of the liquid crystal panel to supply light to the panel.
Recently, the liquid crystal display device has been requested to provide higher-brightness and higher-definition images. In order to meet such a request, high-brightness lamps are provided in the backlight unit. In addition, the lamps are supplied with high lamp current to emit high-brightness light. However, the magnitude of the lamp current to the lamps is in inverse proportion to the service life of the lamps. That is, if the lamp current is raised to obtain high brightness, the service life of the lamps is disadvantageously shortened. Conversely, if the lamp current is reduced to lengthen the service life of the lamps, the brightness of the lamps is disadvantageously lowered. Moreover, the higher the lamp current to the lamps, the larger the power consumption of the liquid crystal display device.
Accordingly, an adaptive brightness intensification backlight unit has been developed in order to solve the above problem. This adaptive brightness intensification backlight unit is characterized in that the luminance of video data is analyzed, a brightness control signal is generated according to the analyzed luminance, and the lamps are driven by an inverter in response to the generated brightness control signal. That is, the brightness of the lamps is controlled according to the gray scale of the video data, thereby lengthening the service life of the lamps and preventing unnecessary power consumption required to drive the lamps to generate the same brightness as that of a high gray scale image with respect to a low gray scale image.
Next, a description will be given of a conventional liquid crystal display device with an adaptive brightness intensification backlight unit with reference to the annexed drawings.
FIG. 3 is a block diagram showing the configuration of a conventional liquid crystal display device with an adaptive brightness intensification backlight unit.
As shown in FIG. 3, a driving circuit 12 includes an external storage unit 25a for storing data stretching values and backlight dimming control values for adaptive brightness intensification, and a DC-DC converter 24 for receiving a voltage from a system through a connector 22, stepping up or down the received voltage, outputting the resulting drive voltages Vcc and Vdd necessary to respective components, and outputting a gate low voltage signal VGL and a gate high voltage signal VGH in response to an enable signal from a timing controller 23. The timing controller 23 is adapted to, upon power-on, read data stored in the external storage unit (for example, an EEPROM) 25a and allow an adaptive brightness intensifier (AI) circuit 31a therein to analyze an inputted image and perform a data stretching function and a backlight dimming control function on the basis of the read data as a result of the image analysis to lower backlight brightness. The timing controller 23 is also adapted to receive a video signal from the system and output a control signal to drive a liquid crystal panel 11 of the liquid crystal display device. The driving circuit 12 further includes a gate driver 11a for generating a scan pulse in response to the gate high voltage signal VGH and gate low voltage signal VGL, outputted from the DC-DC converter 24 in response to the enable signal from the timing controller 23, and supplying the generated scan pulse sequentially to gate lines G of the liquid crystal panel 11, and a data driver 11b for receiving a video signal outputted from the timing controller 23, digital/analog-converting the received video signal into an analog video signal and supplying the converted analog video signal to each data line D of the liquid crystal panel 11. The driving circuit 12 further includes an inverter 34 for driving a backlight lamp 35 in response to a control signal from the AI circuit 31a. The remaining parts of the driving circuit 12 are the same as those illustrated in FIG. 1.
The AI circuit 31a analyzes the luminance of the inputted video data. The video data is usually inputted in the form of an RGB signal containing red, green and blue image information. This video data is composed of a YUV signal including a luminance signal Y and a chrominance signal (U,V), and the AI circuit 31a detects the luminance signal from the YUV signal. Then, the AI circuit 31a measures a luminance variation for every frame and outputs the resulting control signal to the inverter 34 to adjust the brightness of the backlight lamp 35.
Here, for the convenience of description of communication between the external storage unit 25a and the AI circuit 31a, the external storage unit 25a is expressed as a slave and the AI circuit 31a is expressed as a master.
A look-up table (LUT), the backlight dimming control values and the data stretching values are prestored in the external storage unit 25a, which is the slave as aforementioned. When the liquid crystal display device is powered on, the DC-DC converter 24 generates and supplies various voltages for the driving of the display device. In particular, the DC-DC converter 24 supplies a drive voltage Vcc for data communication between the external storage unit 25a and the AI circuit 31a. 
At this time, the drive voltage Vcc from the DC-DC converter 24 is directly supplied to the external storage unit 25a. 
FIG. 4 is a circuit diagram of an external storage unit of a conventional over-driving circuit or adaptive brightness intensification backlight unit.
In FIG. 4, the external storage unit 25 or 25a of the conventional over-driving circuit (ODC) or adaptive brightness intensifier (AI) circuit may be, for example, an electrically erasable programmable read only memory (EEPROM). A desired look-up table is created and written in the EEPROM by a microcomputer so as to be used for over-driving or adaptive brightness intensification.
The look-up table is created in the following manner.
That is, the look-up table is created by arranging values corresponding to a video signal of a previous frame and a video signal of a current frame inputted from the system through the connector 22 in an x-axis and a y-axis, and inputting a value corresponding to a corrected video signal Do at an intersection of the x-axis and y-axis.
The conventional external storage unit, or EEPROM, 25 or 25a has a plurality of terminals (first to eighth terminals).
The EEPROM is connected to an external microcomputer in a write mode and to the driving circuit of the liquid crystal display device in a liquid crystal module drive mode.
The first to third terminals 1, 2 and 3 are no connection (NC) terminals which are spare terminals applied with no specific data or voltage. These first to third terminals 1, 2 and 3 are connected to a ground voltage VSS along with the fourth terminal 4, which is a ground voltage terminal. In general, the first to third terminals 1, 2 and 3 can replace other terminals to which a power supply voltage or a data or clock signal is applied, when they fail. The first to third terminals 1, 2 and 3 are grounded regardless of the write mode and the liquid crystal module drive mode before replacing other terminals.
The fifth terminal 5 and the sixth terminal 6 receive a data signal SDA and a clock signal SCL from the microcomputer in the write mode, respectively, and receive a supply voltage VCC from an internal supply voltage generator 32 of the liquid crystal display device in the liquid crystal module drive mode.
The seventh terminal 7 is a write control (WC) terminal to which the ground voltage VSS is applied so that the EEPROM 25 or 25a is in a write enable state. This seventh terminal 7 is always applied with the ground voltage VSS regardless of the write mode and the liquid crystal module drive mode.
The eighth terminal 8 is connected to a supply voltage terminal VCC of a connector 40 in the write mode and to the supply voltage VCC in the liquid crystal module drive mode to maintain the EEPROM 25 or 25a in the enable state.
The above-mentioned conventional external storage unit, or EEPROM, 25 or 25a is always maintained in the write enable state because the write control terminal, or seventh terminal 7, is grounded. For this reason, there is a risk that undesired data may be written in the EEPROM or data written in the EEPROM may be lost, due to external factors of a liquid crystal module (LCM), even in the liquid crystal module drive mode after the write mode is performed.
FIGS. 5A and 5B are photographs showing image quality deteriorations which appear on the screen when a malfunction occurs in the write control terminal of the external storage unit.
FIGS. 5A and 5B show poor display states resulting from the fact that undesired data is written into the EEPROM as the EEPROM is maintained in the enable state due to the grounding of the write control terminal of the EEPROM.
In particular, this problem occurs when the over-driving or adaptive brightness intensification is carried out on the basis of a look-up table containing the undesired data written in the EEPROM.
In other words, the above-described conventional liquid crystal display device has disadvantages as follows.
The EEPROM, which is the external storage unit, is always maintained in the write enable state because the write control terminal is always grounded. For this reason, there is a risk that undesired data may be written in the EEPROM due to external factors when the liquid crystal module is driven.
It is thus difficult to secure reliability of the EEPROM.
In addition, a poor display state may occur when the over-driving or adaptive brightness intensification is carried out on the basis of a look-up table containing the undesired data written in the EEPROM. Therefore a need exists to secure the reliability of the EEPROM.